Preface for advanced discrete optimization techniques for VLSI layout problems

An efficient approach for solving layout problems

This paper offers an approach that could be useful for diverse types of layout problems or even area allocation problems. By this approach there is no need to large number of discrete variables and only by few continues variables large-scale layout problems could be solved in polynomial time. This is resulted from dividing area into discrete and continuous dimensions. Also defining decision var...

Advanced Data Layout Optimization for Multimedia Applications

Increasing disparity between processor and memory speeds has been a motivation for designing systems with deep memory hierarchies. Most data-dominated multimedia applications do not use their cache e ciently and spend much of their time waiting for memory accesses [1]. This also implies a signi cant additional cost in increased memory bandwidth, in the system bus load and the associated power c...

Placement Techniques for VLSI Layout Using Sequence-Pair Legalization

This thesis considers the placement problem in VLSI layout, which deals with layout optimization of integrated circuits. Most practical formulations of this problem are NP-hard. The most widely used formulations of this problem consider placement of rectangles within a rectangular container. The rectangles represent logical components and are called modules. Modules are connected by wires and a...

A Framework for Solving VLSI Graph Layout Problems

An Adaptive Parallel Genetic Algorithm for VLSI-Layout Optimization

The generation of a high quality layout during the design of a VLSI microchip is a very complex combinatorial optimization prob lem Components of a circuit have to be placed and signal nets have to be routed on an overall minimal area In this paper a parallel Genetic Algorithm for the combined optimization of placement and routing is presented The main focus is on the self adaptation of the sea...